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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 120 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? high endurance, non-volatile memory segments ? 2k/4k/8k bytes of in-system, self-programmable flash program memory ? endurance: 10,000 write/erase cycles ? 128/256/512 by tes of in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 128/256/512 bytes of internal sram ? data retention: 20 years at 85 c / 100 years at 25 c ? programming lock for self-programming flash & eeprom data security ? peripheral features ? one 8-bit and one 16-bit timer/counter with two pwm channels, each ? 10-bit adc ? 8 single-ended channels ? 12 differential adc channel pairs with programmable gain (1x / 20x) ? programmable watchdog timer wi th separate on-chip oscillator ? on-chip analog comparator ? universal serial interface ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? internal and external interrupt sources ? pin change interrupt on 12 pins ? low power idle, adc noise reductio n, standby and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit with software disable function ? internal calibrated oscillator ? on-chip temperature sensor ? i/o and packages ? available in 20-pin qfn/mlf/vqfn, 14-p in soic, 14-pin pdip and 15-ball ufbga ? twelve programmable i/o lines ? operating voltage: ? 1.8 ? 5.5v ? speed grade: ? 0 ? 4 mhz @ 1.8 ? 5.5v ? 0 ? 10 mhz @ 2.7 ? 5.5v ? 0 ? 20 mhz @ 4.5 ? 5.5v ? industrial temperature range: -40 c to +85 c ? low power consumption ? active mode: ? 210 a at 1.8v and 1 mhz ?idle mode: ? 33 a at 1.8v and 1 mhz ? power-down mode: ? 0.1 a at 1.8v and 25 c 8-bit microcontroller with 2k/4k/8k bytes in-system programmable flash attiny24a attiny44a attiny84a summary rev. 8183fs?avr?06/12
2 8183fs?avr?06/12 attiny24a/44a/84a 1. pin configurations figure 1-1. pinout of attiny24a/44a/84a table 1-1. ufbga - pinout attiny24a/44a/84a (top view) 1234 a pa5 pa6 pb2 b pa4 pa7 pb1 pb3 c pa3 pa2 pa1 pb0 d pa0 gnd gnd vcc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 vcc (pcint8/xtal1/clki) pb0 (pcint9/xtal2) pb1 (pcint11/reset/dw) pb3 (pcint10/int0/oc0a/ckout) pb2 (pcint7/icp/oc0b/adc7) pa7 (pcint6/oc1a/sda/mosi/di/adc6) pa6 gnd pa0 (adc0/aref/pcint0) pa1 (adc1/ain0/pcint1) pa2 (adc2/ain1/pcint2) pa3 (adc3/t0/pcint3) pa4 (adc4/usck/scl/t1/pcint4) pa5 (adc5/do/miso/oc1b/pcint5) pdip/soic 1 2 3 4 5 qfn/mlf/vqfn 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 note bottom pad should be soldered to ground. dnc: do not connect dnc dnc gnd vcc dnc pa7 (pcint7/icp/oc0b/adc7) pb2 (pcint10/int0/oc0a/ckout) pb3 (pcint11/reset/dw) pb1 (pcint9/xtal2) pb0 (pcint8/xtal1/clki) pa 5 dnc dnc dnc pa 6 pin 16: pa6 (pcint6/oc1a/sda/mosi/di/adc6) pin 20: pa5 (adc5/do/miso/oc1b/pcint5) (adc4/usck/scl/t1/pcint4) pa4 (adc3/t0/pcint3) pa3 (adc2/ain1/pcint2) pa2 (adc1/ain0/pcint1) pa1 (adc0/aref/pcint0) pa0
3 8183fs?avr?06/12 attiny24a/44a/84a 1.1 pin descriptions 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb3:pb0) port b is a 4-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability except pb3 which has the reset capability. to use pin pb3 as an i/o pin, instead of reset pin, program (?0?) rstdisbl fuse. as inpu ts, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny24a/44a/84a as listed in section 10.2 ?alternate port functions? on page 58 . 1.1.4 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and prov ided the reset pin has not been disabled. the min- imum pulse length is given in table 20-4 on page 176 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1.1.5 port a (pa7:pa0) port a is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a has alternate functions as analog inputs for the adc, analog com parator, timer/counter, spi and pin change interrupt as described in ?alternate port functions? on page 58 .
4 8183fs?avr?06/12 attiny24a/44a/84a 2. overview attiny24a/44a/84a are low-power cmos 8-bit microcontrollers based on the avr enhanced risc architecture. by executing powerful in structions in a single clock cycle, the attiny24a/44a/84a achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arit hmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. watchdog timer mcu control register timer/ counter0 data dir. reg.port a data register port a programming logic timing and control mcu status register port a drivers pa[7:0] vcc gnd + _ analog comparator 8-bit databus adc isp interface interrupt unit eeprom internal oscillator oscillators calibrated oscillator internal data dir. reg.port b data register port b port b drivers pb[3:0] program counter stack pointer program flash sram general purpose registers instruction register instruction decoder status register z y x alu control lines timer/ counter1
5 8183fs?avr?06/12 attiny24a/44a/84a the attiny24a/44a/84a provides the following features: 2k/4k/8k byte of in-system program- mable flash, 128/256/512 by tes eeprom, 128/256/512 bytes sram, 12 general purpose i/o lines, 32 general purpose working registers, an 8-bit timer/counter with two pwm channels, a 16-bit timer/counter with two pw m channels, internal and external interrupts, a 8-channel 10-bit adc, programmable gain stage (1x, 20x) for 12 differential adc channel pairs, a programmable watchdog timer with internal oscillator, internal ca librated oscillator, and four software select- able power saving modes. idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. adc noise reduction mode minimizes switching noise during adc conv ersions by stopping the cpu and all i/o mod- ules except the adc. in power-down mode registers keep their contents and all chip functions are disbaled until the next inte rrupt or hardware reset. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allo wing very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on- chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny24a/44a/84a avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers , program debugger/simulators and evaluation kits.
6 8183fs?avr?06/12 attiny24a/44a/84a 3. general information 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for downloa d at http://www.a tmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in the extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically, this means ?lds? and ?sts? combined with ?sbrs?, ?s brc?, ?sbr?, and ?cbr?. note that not all avr devices include an extended i/o map. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfaces on atmel avr microcontrollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisi- tion methods. touch sensing is easily added to any application by linking the qtouch library and using the application programming interface (api) of the library to define the touch channels and sensors. the application then calls the api to retrieve ch annel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more informa- tion and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results sh ow that the projected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 3.5 disclaimer typical values contained in th is datasheet are based on simula tions and characterization of other avr microcontrollers manufactured on th e same process technology. min and max values will be available after the devi ce has been characterized.
7 8183fs?avr?06/12 attiny24a/44a/84a 4. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c page 14 0x3e (0x5e) sph ? ? ? ? ? ? sp9 sp8 page 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 13 0x3c (0x5c) ocr0b timer/counter0 ? output compare register b page 83 0x3b (0x5b) gimsk ? int0 pcie1 pcie0 ? ? ? ? page 50 0x3a (0x5a) gifr ? intf0 pcif1 pcif0 ? ? ? ? page 51 0x39 (0x59) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 page 83 0x38 (0x58) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 page 84 0x37 (0x57) spmcsr ? ? rsig ctpb rflb pgwrt pgers spmen page 156 0x36 (0x56) ocr0a timer/counter0 ? output compare register a page 83 0x35 (0x55) mcucr bods pud se sm1 sm0 bodse isc01 isc00 pages 36 , 50 , 66 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 44 0x33 (0x53) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 82 0x32 (0x52) tcnt0 timer/counter0 page 83 0x31 (0x51) osccalcal7cal6cal5cal4cal3cal2cal1cal0 page 31 0x30 (0x50) tccr0a com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 page 79 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 page 106 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 108 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte page 110 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte page 110 0x2b (0x4b) ocr1ah timer/counter1 ? compare register a high byte page 110 0x2a (0x4a) ocr1al timer/counter1 ? compare register a low byte page 110 0x29 (0x49) ocr1bh timer/counter1 ? compare register b high byte page 110 0x28 (0x48) ocr1bl timer/counter1 ? compare register b low byte page 110 0x27 (0x47) dwdr dwdr[7:0] page 151 0x26 (0x46) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 31 0x25 (0x45) icr1h timer/counter1 - input capture register high byte page 111 0x24 (0x44) icr1l timer/counter1 - input capture register low byte page 111 0x23 (0x43) gtccr tsm ? ? ? ? ? ? psr10 page 114 0x22 (0x42) tccr1c foc1a foc1b ? ? ? ? ? ? page 109 0x21 (0x41) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 page 44 0x20 (0x40) pcmsk1 ? ? ? ? pcint11 pcint10 pcint9 pcint8 page 51 0x1f (0x3f) eearh ? ? ? ? ? ? ?eear8 page 20 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 21 0x1d (0x3d) eedr eeprom data register page 21 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 23 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 66 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 66 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 67 0x18 (0x38) portb ? ? ? ? portb3 portb2 portb1 portb0 page 67 0x17 (0x37) ddrb ? ? ? ? ddb3 ddb2 ddb1 ddb0 page 67 0x16 (0x36) pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 page 67 0x15 (0x35) gpior2 general purpose i/o register 2 page 22 0x14 (0x34) gpior1 general purpose i/o register 1 page 23 0x13 (0x33) gpior0 general purpose i/o register 0 page 23 0x12 (0x32) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 page 52 0x11 (0x31)) reserved ? 0x10 (0x30) usibr usi buffer register page 127 0x0f (0x2f) usidr usi data register page 126 0x0e (0x2e) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 page 125 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc page 123 0x0c (0x2c) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 page 111 0x0b (0x2b) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 page 112 0x0a (0x2a) reserved ? 0x09 (0x29) reserved ? 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 page 129 0x07 (0x27) admux refs1 refs0 mux5 mux4 mux3 mux2 mux1 mux0 page 144 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 146 0x05 (0x25) adch adc data register high byte page 148 0x04 (0x24) adcl adc data register low byte page 148 0x03 (0x23) adcsrb bin acme ?adlar ? adts2 adts1 adts0 pages 130 , 148 0x02 (0x22) reserved ? 0x01 (0x21) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d pages 131 , 149 0x00 (0x20) prr ? ? ? ? prtim1 prtim0 prusi pradc page 37
8 8183fs?avr?06/12 attiny24a/44a/84a note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accesse d. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specif ied bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only.
9 8183fs?avr?06/12 attiny24a/44a/84a 5. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
10 8183fs?avr?06/12 attiny24a/44a/84a ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
11 8183fs?avr?06/12 attiny24a/44a/84a 6. ordering information notes: 1. for speed vs. supply voltage, see section 20.3 ?speed? on page 174 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs) 3. code indicators: ? h: nipdau lead finish ? f, n, u: matte tin ? r: tape & reel 4. topside marking for attiny24a: t24 / axx / manufacturing data 5. also supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 6. for typical and electrical characteristics, see ?a ppendix a ? attiny24a/44a specification at 105c?. 7. for typical and electrical characteristics, see ?ap pendix b ? attiny24a/44a/84a specification at 125c?. 6.1 attiny24a speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code (3) 20 1.8 ? 5.5v industrial (-40 c to +85 c) (5) 14s1 attiny24a-ssu attiny24a-ssur 14p3 attiny24a-pu 15cc1 attiny24a-ccu attiny24a-ccur 20m1 attiny24a-mu attiny24a-mur 20m2 attiny24a-mmh (4) attiny24a-mmhr (4) industrial (-40 c to +105 c) (6) 14s1 attiny24a-ssn attiny24a-ssnr industrial (-40 c to +125 c) (7) 14s1 attiny24a-ssf attiny24a-ssfr 20m1 attiny24a-mf attiny24a-mfr 20m2 attiny24a-mm8 attiny24a-mm8r package type 14s1 14-lead, 0.150" wide body, plastic gull wing small outline package (soic) 14p3 14-lead, 0.300" wide, plastic dual inline package (pdip) 15cc1 15-ball (4 x 4 array), 0.65 mm pitch, 3.0 x 3.0 x 0.6 mm , ultra thin, fine-pitch ball grid array package (ufbga) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no lead / micro lead frame package (qfn/mlf) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn)
12 8183fs?avr?06/12 attiny24a/44a/84a notes: 1. for speed vs. supply voltage, see section 20.3 ?speed? on page 174 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). 3. code indicators: ? h: nipdau lead finish ? f, n, u: matte tin ? r: tape & reel 4. topside marking for attiny44a: ? 1st line: t44 ? 2nd line: axx ? 3rd line: manufacturing data 5. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 6. for typical and electrical characteristics, see ?a ppendix a ? attiny24a/44a specification at 105c?. 7. for typical and electrical characteristics, see ?ap pendix b ? attiny24a/44a/84a specification at 125c?. 6.2 attiny44a speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code (3) 20 1.8 ? 5.5v industrial (-40 c to +85 c) (5) 14s1 attiny44a-ssu attiny44a-ssur 14p3 attiny44a-pu 15cc1 attiny44a-ccu attiny44a-ccur 20m1 attiny44a-mu attiny44a-mur 20m2 attiny44a-mmh (4) attiny44a-mmhr (4) industrial (-40 c to +105 c) (6) 14s1 attiny44a-ssn attiny44a-ssnr industrial (-40 c to +125 c) (7) 14s1 attiny44a-ssf attiny44a-ssfr 20m1 attiny44a-mf attiny44a-mfr package type 14s1 14-lead, 0.150" wide body, plastic gull wing small outline package (soic) 14p3 14-lead, 0.300" wide, plastic dual inline package (pdip) 15cc1 15-ball (4 x 4 array), 0.65 mm pitch, 3.0 x 3.0 x 0.6 mm , ultra thin, fine-pitch ball grid array package (ufbga) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no lead / micro lead frame package (qfn/mlf) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn)
13 8183fs?avr?06/12 attiny24a/44a/84a notes: 1. for speed vs. supply voltage, see section 20.3 ?speed? on page 174 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). 3. code indicators: ? h: nipdau lead finish ? f, n, u: matte tin ? r: tape & reel 4. topside marking for attiny84a: ? 1st line: t84 ? 2nd line: axx ? 3rd line: manufacturing data 5. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 6. for typical and electrical characteristics, see ?a ppendix a ? attiny24a/44a specification at 105c?. 7. for typical and electrical characteristics, see ?ap pendix b ? attiny24a/44a/84a specification at 125c?. 6.3 attiny84a speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code (3) 20 1.8 ? 5.5v industrial (-40 c to +85 c) (5) 14s1 attiny84a-ssu attiny84a-ssur 14p3 attiny84a-pu 15cc1 attiny84a-ccu attiny84a-ccur 20m1 attiny84a-mu attiny84a-mur 20m2 attiny84a-mmh (4) attiny84a-mmhr (4) industrial (-40 c to +125 c) (7) 14s1 attiny84a-ssf ATTINY84A-SSFR package type 14s1 14-lead, 0.150" wide body, plastic gull wing small outline package (soic) 14p3 14-lead, 0.300" wide, plastic dual inline package (pdip) 15cc1 15-ball (4 x 4 array), 0.65 mm pitch, 3.0 x 3.0 x 0.6 mm , ultra thin, fine-pitch ball grid array package (ufbga) 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no lead / micro lead frame package (qfn/mlf) 20m2 20-pad, 3 x 3 x 0.85 mm body, very thin quad flat no lead package (vqfn)
14 8183fs?avr?06/12 attiny24a/44a/84a 7. packaging information 7.1 14s1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 14 s 1 , 14-lead, 0.150" w ide body, plastic g u ll w ing small o u tline package (soic) 2/5/02 14s1 a a1 e l side v iew top v iew end v iew h e b n 1 e a d common dimen s ion s (unit of meas u re = mm/inches) s ymbol min nom max note n otes: 1. this drawing is for general information only; refer to jedec drawing ms-012, v ariation ab for additional information. 2. dimension d does not incl u de mold flash, protr u sions or gate bu rrs. mold flash, protr u sion and gate bu rrs shall not exceed 0.15 mm (0.006") per side. 3. dimension e does not incl u de inter-lead flash or protr u sion. inter-lead flash and protr u sions shall not exceed 0.25 mm (0.010") per side. 4. l is the length of the terminal for soldering to a s ub strate. 5. the lead width b, as meas u red 0.36 mm (0.014") or greater a b ove the seating plane, shall not exceed a maxim u m val u e of 0.61 mm (0.024") per side. a 1.35/0.0532 ? 1.75/0.06 88 a1 0.1/.0040 ? 0.25/0.009 8 b 0.33/0.0130 ? 0.5/0.0200 5 d 8 .55/0.3367 ? 8 .74/0.3444 2 e3. 8 /0.1497 ? 3.99/0.1574 3 h5. 8 /0.22 8 4 ? 6.19/0.2440 l 0.41/0.0160 ? 1.27/0.0500 4 e 1.27/0.050 bsc
15 8183fs?avr?06/12 attiny24a/44a/84a 7.2 14p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 14p3 , 14-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 14p3 2010-10-20 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 18.669 ? 19.685 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.143 ? 1.778 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation aa. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 8183fs?avr?06/12 attiny24a/44a/84a 7.3 15cc1 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com r c cbc 15cc1, 15-ball (4 x 4 array), 3.0 x 3.0 x 0.6 mm package, ball pitch 0.65 mm, ultra thin, fine-pitch ball grid array package (ufbga) 15cc1 07/06/10 a ? ? 0.60 a1 0.12 ? ? a2 0.38 ref b 0.25 0.30 0.35 1 b1 0.25 ? ? 2 d 2.90 3.00 3.10 d1 1.95 bsc e 2.90 3.00 3.10 e1 1.95 bsc e 0.65 bsc common dimensions (unit of measure = mm) symbol min nom max note top view 123 4 a b c d e d 15-?b d c b a pin#1 id 0.08 a1 a d1 e1 a2 a1 ball corner e 123 4 side view b1 bottom view e note1: dimension ?b? is measured at the maximum ball dia. in a plane parallel to the seating plane. note2: dimension ?b1? is the solderable surface defined by the opening of the solder resist layer.
17 8183fs?avr?06/12 attiny24a/44a/84a 7.4 20m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20m1 , 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0.50 mm, b 20m1 10/27/04 2.6 mm exposed pad, micro lead frame package (mlf) a 0.70 0.75 0.80 a1 ? 0.01 0.05 a2 0.20 ref b 0.18 0.23 0.30 d 4.00 bsc d2 2.45 2.60 2.75 e 4.00 bsc e2 2.45 2.60 2.75 e 0.50 bsc l 0.35 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec standard mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of measure = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.08 c l 1 2 3 b 1 2 3
18 8183fs?avr?06/12 attiny24a/44a/84a 7.5 20m2 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 20m2 zfc b 20m2, 20-pad, 3 x 3 x 0.85 mm body, lead pitch 0.45 mm, 1.55 x 1.55 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/08 15 14 13 12 11 1 2 3 4 5 16 17 18 19 20 10 9 8 7 6 d2 e2 e b k l pin #1 chamfer (c 0.3) d e side view a1 y pin 1 id bottom view top view a1 a c c0.18 (8x) 0.3 ref (4x) common dimensions (unit of measure = mm) symbol min nom max note a 0.75 0.80 0.85 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.152 d 2.90 3.00 3.10 d2 1.40 1.55 1.70 e 2.90 3.00 3.10 e2 1.40 1.55 1.70 e ? 0.45 ? l 0.35 0.40 0.45 k 0.20 ? ? y 0.00 ? 0.08
19 8183fs?avr?06/12 attiny24a/44a/84a 8. errata the revision letters in this section refer to t he revision of the corresponding attiny24a/44a/84a device. 8.1 attiny24a 8.1.1 rev. h no known errata. 8.1.2 rev. g not sampled. 8.1.3 rev. f not sampled. 8.2 attiny44a 8.2.1 rev. g no known errata. yield improvement. 8.2.2 rev. f no known errata. 8.2.3 rev. e not sampled. 8.3 attiny84a 8.3.1 rev. c no known errata.
20 8183fs?avr?06/12 attiny24a/44a/84a 9. datasheet revision history 9.1 rev. 8183f ? 06/12 1. updated: ? table 16-1 on page 138 ? figure 16-7 on page 137 ? ?ordering information? on page 11 9.2 rev. 8183e ? 01/12 1. updated: ? production status for attiny24a and attiny84a ? ?start condition detector? on page 122 ? ?ordering information? on page 11 , 12 , and 13 9.3 rev. 8183d ? 04/11 1. added errata for attiny44a rev. g in section 8. ?errata? on page 19 9.4 rev. 8183c ? 03/11 1. added: ? attiny84a, including typical characteristics plots ? section 3.3 ?capacitive touch sensing? on page 6 ? table 6-8, ?capacitance of low-frequency crystal oscillator,? on page 28 ? analog comparator offset plots for attiny24a ( figure 21.2.10 on page 208 ) and attiny44a ( figure 21.3.11 on page 236 ) ? extended temperature part numbers in section 6. ?ordering information? on page 11 2. updated: ? bit syntax throughout the datasheet, e.g. from cs02:0 to cs0[2:0] ? section 6.4 ?clock output buffer? on page 30 , changed clko to ckout ? table 16-4, ?single-ended input channel selections,? on page 145 , added note for internal 1.1v reference ? table 19-16, ?high-voltage serial programming instruction set for attiny24a/44a/84a,? on page 170 , adjusted notes ? table 20-1, ?dc characteristics. ta = -40c to +85c,? on page 173 , adjusted notes 9.5 rev. 8183b ? 03/10 1. updated template. 2. added ufbga package (15cc1) in: ?features? on page 1 , ?pin configurations? on page 2 , section 6. ?ordering information? on page 11 , and section 7.3 ?15cc1? on page 16 . 3. separated typical characteristic plots, added section 21.2 ?attiny24a? on page 183 . 4. updated sections: ? section 14.5.4 ?usibr ? usi buffer register? on page 127 , header updated
21 8183fs?avr?06/12 attiny24a/44a/84a ? section 6. ?ordering information? on page 11 , added tape & reel and topside marking, updated notes 5. updated figures: ? figure 4-1 ?block diagram of the avr architecture? on page 7 ? figure 8-1 ?reset logic? on page 38 ? figure 14-1 ?universal serial interface, block diagram? on page 116 , usidb -> usibr ? figure 19-5 ?high-voltage serial programming waveforms? on page 169 6. updated tables: ? table 19-11, ?minimum wait delay before writing the next flash or eeprom location,? on page 164 , updated value for t wd_erase 9.6 rev. 8183a ? 12/08 1. initial revision. created from document 8006h. 2. updated "ordering information" on page 19 and page 19 . pb-plated packages are no longer offered and there are no separate ordering codes for commercial operation range, the only available option now is indu strial. also, updated some order codes to reflect changes in leadframe composit ion and added vqfn package option. 3. updated data sheet template. 4. removed all references to 8k device. 5. updated characteristic pl ots of section ?typical ch aracteristics?, starting on page 182 . 6. added characteristic plots: ? ?bandgap voltage vs. supply voltage? on page 233 ? ?bandgap voltage vs. temperature? on page 233 7. updated sections: ? ?features? on page 1 ? ?power reduction register? on page 35 ? ?analog comparator? on page 128 ? ?features? on page 132 ? ?operation? on page 133 ? ?starting a conversion? on page 134 ? ?adc voltage reference? on page 139 ? ?speed? on page 174 8. updated figures: ? ?program memory map? on page 15 ? ?data memory map? on page 16 9. update tables: ? ?device signature bytes? on page 161 ? ?dc characteristics. ta = -40c to +85c? on page 173 ? ?additional current consumption for the different i/o modules (absolute values)? on page 182 ? ?additional current consumption (percentage) in active and idle mode? on page 183
8183fs?avr?06/12 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81)(3) 3523-3551 fax: (+81)(3) 3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection wi th atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including , but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indire ct, consequential, punitive, special or i nciden- tal damages (including, without li mitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of th is document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2012 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. o ther terms and product names may be trademarks of others.

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